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Terabits ATM Switch with Optical Interconnection Network


Terabit/s ATM Switch with Optical Interconnection Network
H. Jonathan Chao, Jin-Soo Park, and Ti-Shiang Wang Polytechnic University, USA.
We proposed a Terabit/s ATM switch architecture by interconnecting multiple small switch modules with an optical interconnection network. A new cell contention resolution scheme is devised to achieve 100% throughput and to meet the speed requirement of 1 Terabit/s.

Abstract

Correspondence Address: H. Jonathan Chao Polytechnic University Department of Electrical Engineering 6 Metrotech Center Brooklyn, New York 11201 TEL: (718)260-3302, FAX: (718)260-3074 E-mail: chao@antioch.poly.edu

Terabit/s ATM Switch with Optical Interconnection Network
H. Jonathan Chao, Jin-Soo Park, and Ti-Shiang Wang Polytechnic University, Department of Electrical Engineering 6 Metrotech Center, Brooklyn, New York 11201. Email:chao@antioch.poly.edu, jspark@acts.poly.edu, tswang@acts.poly.edu

An ATM switch with capacity up to 1 Tb=s will be required in the future to meet the exponential growth of Internet tra c. Although an electronic ATM switch module with 10Gb=s is commercially available, how to interconnect multiple of them to build up a large capacity switch remains challenging. Here, we present an optical interconnection network (OIN) to interconnect multiple 10Gb=s ATM switch modules with interconnection bers running at 10Gb=s, as shown in Figure 1. Cells are stored in the input switch modules (ISM) and scheduled to transmit through the OIN by an electronic controller, where arbitration of output contention is performed. We take the advantage of the advance of wavelength-division-multiplexing (WDM) technology to construct the OIN, where optical devices, such as wavelength converters (WC) and tunable lters (TF), are used. We propose a new arbitration algorithm to resolve output contention, which is capable of handling more than 1 Tb/s tra c. Each ISM has a request arbiter and N logical queues; each associated with an output switch module (OSM). Each request arbiter chooses a nonempty logical queue based on its pointer value, which points to the logical queue that has the the highest service priority. After selection, each ISM sends at most one request (or none) to a central scheduler, which has N grant arbiters, one for each OSM. Each grant arbiter may receive up to N requests and chooses one ISM among the requests based on a pointer value that points to the ISM that has the highest service priority. After the N grant arbiters simultaneously made their selections, the central scheduler sends the grant signals to ISMs. The pointer values of the request and grant arbiters change dynamically and are updated to the value of which its proceeding logical queue or ISM was just selected. Because both the request and grant arbiters perform the arbitration in a round-robin fashion, the arbitration scheme is called the Dual Round Robin Matching (DRRM). Updating the pointer values of request arbiters upon receiving the grant signals desynchronize the arbiters. Request arbiters that are granted in the previous time slot will have di erent pointer values. Thus, they will each request to di erent outputs afterwards. Let us consider a 2 2 switch. Let us assume that both ISMs have cells destined for both OSMs and that the pointer values of both request arbiters (RA) are 1 and the pointer values of both grant arbiters (GA) are also 1. At the beginning, both ISMs may request OSM1 and the grant arbiter of OSM1 may grant to ISM1; in this case only one connection will be made in the current time slot. RA1 increases its pointer value to 2 and so does GA1 . In the next time slot, these two ISMs no longer contend to the same OSM because request arbiters become desynchronized with each other.This can lead to a maximum throughput of 100% as shown in Figure 2. A similar arbitration scheme, iSLIP, has been proposed by McKeown et al. 1]. However, the DRRM is simpler and requires less time to complete the arbitration while achieving comparable performance (see Figure 2). The arbitration cycle consists of the time to pass the signals from the request arbiters to the grant arbiters and vise verse, and the time to process the arbitration. The function performed by both the request arbiters and grant arbiters is identical, which is N -to1 priority encoding and can easily be implemented by using existing technology while meeting our timing requirement.

The delay performance of the DRRM can be improved by increasing the OIN's operation speed. For instance, as the speed-up factor, S , is equal to 2, the delay performance is very close to the optimal value of output bu ering (see in Figure 2). However, increasing the OIN's operation speed from 10Gb=s to 20Gb=s will not only increase the technology di culty for electronic interface components and optical devices, but also reduces the arbitration time to a half of a cell slot time, 21 ns, which may cause the bottleneck for a large-scale switch. To reduce the interconnection complexity of the 128 128 ATM switch, every 8 input
Optical Interconnection Network
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Figure 1: Proposed ATM switch

Mux: multiplexer ISM(OSM): input(output) switch module Demux: demultiplexer WC: wavelength converter TF: tunable filter

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lines and every 8 output lines are grouped, resulting in 16 transmitter modules and 16 receiver modules, respectively. Wavelength converters in the transmitter modules are used to convert the incoming wavelength to di erent wavelengths in order to avoid wavelength contention in the same group. The proposed OIN performs the same function as a 3-stage Clos network. To meet the strictly nonblocking requirement, the tunable wavelength converters and tunable lters have to be able to accommodate at least 15 wavelengths. If we let W be the number of available wavelengths and set to 16, the quantity of tunable N lters, Q, in the middle stage of OIN, is equal to 4W 22 , or 256 for N = 128 and W = 16. Because the technology of wavelength converters and tunable lters are still immature at present to support 16 wavelengths conversion and ltering operation at 10Gb=s per channel, tunable lters can be replaced by a wavelength demultiplexer and fast optical gates 2], while tunable wavelength conversion function can be implemented by using fast selectable laser arrays 3].

Figure 2: Average cell dalay at input bu ers versus tra c load

References
1] N. McKeown et al, IEE Electronics letters , pp. 2174-2175, 1993. 2] O. Ishida et al, J. Lightwave Technol. , Vol. 15, No. 2, pp. 321-327, 1997. 3] M. G. Young et al, OSA Proc. Optic. Ampli ers Appli. , pp. 33-37, 1992.


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