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Refinement strategies for verification methods based on datapath abstraction

Refinement Strategies for Verification Methods Based on Datapath Abstraction
Zaher S. Andraus, Mark H. Liffiton, and Karem A. Sakallah
Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI 48109-2122 {zandrawi,liffiton,karem}@eecs.umich.edu

Abstract—In this paper we explore the application of Counterexample-Guided Abstraction Refinement (CEGAR) in the context of microprocessor correspondence checking. The approach utilizes automatic datapath abstraction augmented with automatic refinement based on 1) localization, 2) generalization, and 3) minimal unsatisfiable subset (MUS) extraction. We introduce several refinement strategies and empirically evaluate their effectiveness on a set of microprocessor benchmarks. The data suggest that localization, generalization, and MUS extraction from both the abstract and concrete models are essential for effective verification. Additionally, refinement tends to converge faster when multiple MUses are extracted in each iteration. I. INTRODUCTION

Counterexample-Guided Abstraction Refinement (CEGAR for short) has been shown to be an effective paradigm in a variety of hardware and software verification scenarios. Originally pioneered by Kurshan [16], it has since been adopted by several researchers as a powerful means for coping with verification complexity. The widespread use of such a paradigm hinges, however, on the automation of its abstraction and refinement phases. Without automation, CEGAR requires laborious user intervention to choose the right abstractions and refinements based on a detailed understanding of the intricate interactions among the components of the design being verified. Clarke et al. [9], Jain et al. [14], and Dill et al. [5] have successfully demonstrated the automation of abstraction and refinement in the context of model checking for safety properties of hardware and software systems. In particular, these approaches create a smaller abstract transition system from the underlying concrete transition system and iteratively refine it with the spurious counterexamples produced by the model checker. The approaches in [9] and [14] are additionally based on the extraction of unsatisfiability explanations derived from the infeasible counterexamples to provide stronger refinement of the abstract model and to significantly reduce the number of refinement iterations. All of these approaches are examples of predicate abstraction which, essentially, projects the concrete model onto a given set of relevant predicates to produce an abstraction suitable for model checking a given property. In contrast, Andraus et al. [2] describe a methodology for datapath

abstraction that is particularly suited for equivalence checking. In their approach, datapath components in behavioral Verilog models are automatically abstracted to uninterpreted functions and predicates while refinement is performed manually using the ACL2 theorem prover [15]. The use of (near)-minimal explanations of unsatisfiability forms the basis of another class of abstraction methods. These include the work of Gupta et al. [12] and McMillan et al. [20] who employ “proof analysis” techniques to create an abstraction from an unsatisfiable concrete bounded model checking (BMC) instance of a given depth. In this paper we explore the application of CEGAR in the context of microprocessor correspondence checking. The approach is based on automatic datapath abstraction as in [2] augmented with automatic refinement using minimal unsatisfiable subset (MUS) extraction. One of our main conclusions is the necessity of basing refinement on the extraction of MUSes from both the abstract and concrete models. Additionally, refinement tends to converge faster when multiple MUSes are extracted in each iteration. Finally, localization and generalization of the spurious counterexamples are shown to be crucial for fast convergence of the refinement iteration. The rest of the paper is organized in 4 sections. Section II reviews the basic CEGAR algorithm and describes the various refinement strategies that can be deployed to enhance its performance. Section III briefly describes datapath abstraction and illustrates the abstraction and various refinement steps on a simple example. In Section IV we describe our implementation of these ideas in the Reveal system and discuss the effectiveness of the various refinement options in the verification of a sample benchmark. We conclude in Section V, with a recap of the paper’s main contributions and suggestions for further work.

A sketch of the basic counterexample-guided abstraction refinement methodology is shown in Algorithm 1. The detailed design is assumed to be characterized by a system of concrete constraints conc X 1 i nC i X where X denotes a suitable vector of variables and

C i X is a Boolean consistency constraint that models a particular component in the design. For example, a 32bit adder with inputs A, B, and output S would be represented by the constraint C(A, B, S) = (S = A + B). The verification objective can also be expressed as a Boolean function of the design’s variables. In general we will be concerned with equivalence between signal pairs, but any safety property can be handled similarly. Let prop X denote the condition that we would like to check for on the design. The verification task can be expressed as showing that conc X prop X is valid, i.e., that it is a tautology. CEGAR starts, in line 1, with the construction of an abstraction such that abst X 1 i nAi X

Algorithm 1 (Basic CEGAR)
1. abst(X) = relax(conc(X)) 2. while (true) { 3. if abst(X) -> prop(X) 4. then {“property holds”; exit} 5. else {// abst(X*) -> prop(X*) == 0 6. if conc(X*) 7. then {“property fails”; exit} 8. else // spurious counter example 9. abst(X) = abst(X) && !X*; 10. }// else(line 5) 11. }// while(line 2)

Algorithm 2 (CEGAR with enhanced refinement)
1. abst(X) = relax(conc(X)) 2. while (true) { 3. if abst(X) -> prop(X) 4. then {“property holds”; exit} 5. else {// abst(X*) -> prop(X*) = 0 5a. viol(X) = localize(X*); 5b. viol(X) = generalize(viol(X)); 5c. expl(X) = MUS(!abst(X) && viol(X)); 5d. viol(X) = viol(X) && expl(X); 6. if conc(X) && viol(X) 7. then {“property fails”; exit} 8. else // spurious violation 8a. while (expl(X) = newMUS(conc(X)&& viol(X))) 9. abst(X) = abst(X) && !(viol(X) && expl(X)); 10. }// else(line 5) 11. }// while(line 2)

Ci X Ai X . In other words, each constraint in abst(X) is a relaxation of a corresponding constraint in conc(X)1. This type of abstraction, is sound, i.e., if prop(X) holds on abst(X), then it must also hold on conc(X) (line 4), but incomplete, i.e., prop(X) may be violated on abst(X) but still hold on conc(X)). Completeness is achieved by refining abst(X) to eliminate such cases. Specifically, if X* denotes an assignment of values to variables such that
abst X * prop X * 0 and conc X * 0

equality and dis-equality between pairs of variables. These relations can now be viewed as a conjunction of violation constraints viol(X) that satisfy

then X* represents a spurious counterexample that must be eliminated from the space of consistent assignments in the abstract model (line 9). Note that this process is guaranteed to converge assuming that the abstraction is finite and noting that it shrinks monotonically with each refinement iteration. This basic version of CEGAR can be quite inefficient, requiring a large number of refinement iterations, since false counterexamples are eliminated one at a time. The improved version depicted in Algorithm 2 employs several techniques aimed at reducing the number of refinement iterations. The common goal of these techniques is to use the specific counterexample that falsifies the property on the abstract model as a seed to generate a large collection of “related” counterexamples that can then be simultaneously checked on the concrete model and, subsequently, eliminated at the same time from the abstract model. Algorithm 2 employs the following violation enlargement methods: Localization (line 5a) is basically a cone-of-influence (COI) reduction that removes irrelevant (don’t-care) assignments from the counterexample by a syntactic traversal of the abstract formula. Generalization (line 5b) replaces the specific values of the variables in the counterexample with appropriate

abst X

prop X

viol X


Minimal Unsatisfiable Subset (MUS) extraction (line 5c) selects a small subset of the constraints from the 2 unsatisfiable formula abst X that is viol X still sufficient to explain its infeasibility. Denoting this subset as expl(X), the set of violation constraints is now reduced by eliminating from it those constraints that are not in expl(X) (line 5d). At this point, viol(X) represents not just one but many specific counterexamples that violate prop(X) but are consistent with abst(X). The enlargement of X* to viol(X) was based solely on information from the abstract model and the property being checked. The check in line 6 is now used to determine if any of these violations is consistent with the concrete model. Failing this check implies that all of these violations are spurious and we can refine the abstract model by removing them. However, an additional enhancement (lines 8a and 9) makes it possible to utilize the concrete constraints to enlarge viol(X) further. Specifically, a small number of MUSes from the unsatisfiable formula conc X viol X are extracted and used to select subsets of viol(X) each of which is sufficient to keep the formula unsatisfiable.

In general, both design variables and the concrete constraints that relate them are relaxed.

Note that abst X abst X viol X

prop X 0.

viol X

0 implies that

module example(); wire [3:0] a, b; wire m = a[3]; // msb wire l = a[0]; // lsb wire c = m? a >> 1 : a; wire d = l? b >> 2 : c; wire e = m? a : a >> 1; wire f = l? {2’b00, b[3:2]} : e; wire p = !(a == 0) || (d == f); endmodule;

the concrete constraints of this design is written by inspection as

conc a, b, c, d, e, f , l, m, p m l m l m l p d (e (f a a[3] a[0] c b a) 0 a 2 m d 1 l e f m (d a l (c c) 1 (f e) a)

Fig. 1. Verilog design example used to illustrate abstraction and refinement III.



2 ' b00, b[3 : 2] )

The focus of our work is the application of the CEGAR framework, particularly the afore-mentioned enhanced refinement strategies, in the context of hardware correspondence checking. Specifically, we address the task of verifying that an optimized microprocessor implementation is compliant with its functional specification. The implementation and specification are assumed to be given using a hardware description language, such as Verilog, and together are regarded as the concrete model. The correctness criterion, i.e., the property that must hold to insure that the implementation is functionally equivalent to the specification, depends on the nature of the optimizations performed to obtain the implementation. In particular, pipelined implementations require alignment of the programmer-visible implementation and specification states which can be accomplished, for example, by flushing [8]. The specifics of the correctness criterion, while important, are orthogonal to the abstraction refinement flow and can be assumed, for our purposes, to be provided by the user along with the specification and implementation. The concrete model is relaxed by treating datapath elements as uninterpreted functions (UFs) and uninterpreted predicates (UPs) that operate on unbounded terms [6]. This is justified by the fact that, generally speaking, design optimizations add significant complexity to an implementation’s control logic while, mostly, preserving its datapath components. Datapath abstraction, thus, yields a compact representation that preserves the control interactions in the concrete model while maintaining functional consistency of the abstracted datapath elements. The resulting abstract model can now be viewed as a set of constraints—a formula—in CLU, a quantifier-free first-order logic with counter arithmetic and lambda expressions [6], and used in lieu of the detailed bit-level concrete model to check satisfaction of the desired correctness condition. To illustrate the salient features of datapath abstraction refinement consider the example Verilog “design” in Fig. 1. The verification objective is to prove that signal p is always true, indicating that the design satisfies the condition a 0 d f . The formula representing

Using the semantics of bit vector operations, such as extraction, concatenation, and shifting, along with the standard Boolean connectives, this formula can be translated in a straightforward fashion to propositional conjunctive normal form (CNF) so that it can be checked for satisfiability by standard SAT solvers. In fact, for this simple example it is quite easy for a modern SAT solver p is unsatisfiable which is the to prove that conc p is valid. same as saying that conc Our objective, however, is to establish this result using CEGAR. A possible abstraction of this design is:

abst a, b, c, d, e, f , l, m, s, t, u, p, zero m l s t u c d e f p EX1(a ) EX2(a ) SR1(a, succ(zero)) SR2(b, succ(succ(zero))) CT1(zero, EX3(b)) ite(m, s, a ) ite(l , t, c ) ite(m, a, s ) ite(l , u ,e ) a zero d f

where detailed bit vector operations have been replaced by UP and UF symbols. For example, EX1 is a UP that corresponds to extracting the most significant bit of a, and SR2 is a UF that corresponds to a right shift of b by two bits. Variables in this abstract formula that correspond to bit vectors in the concrete formula are now considered to be unbounded terms. They can be compared for equality to enforce functional consistency (given two terms t1 and t2 and a single-argument UF F, t1 t2 F t1 F t2 ) but are otherwise uninterpreted having lost their concrete semantics. On the other hand, variables in the abstract formula that correspond to single bits in the concrete formula (such as m

a=0 b=8 c = 16 d = 20 e =0 f = 12 l=1 m=1 s = 16 t = 20 u = 12

Iteration 2 Generalize X*
a=0 b = 16 c=8 d=8 e=0 f=0 l=0 m=1 s=8 t=3 u=3

Find MUS


minimal explanation “shifting zeros yields zeros!” The concrete formula was thus able to remove the constraints l = 0 and t = u as irrelevant to the current violation. When this violation is eliminated, by refining with a 0 (a s ) , the algorithm terminates proving that p is always true.


a=0 a=0 a=0 b=8 l=1 l=1 t u t u d = 20 f = 12 l=1

t = 20 u = 12

a=0 b = 16 c=8 d=8 e=0 f=0 l=0 m=1 s=8 t=3 u=3

a=0 l=0 m=1 t=u a s

a=0 l=0 t=u a s



viol1 = (a = 0) (a[0] = 1) viol3 = (a = 0) viol2 = b 2 {2’b00,b[3:2]}




and l) retain their Boolean semantics and can be combined with the standard Boolean connectives. The remaining symbols in the formula represent the CLU built-in functions for counting (succ), decision (if-thenelse or ite) and the smallest term (zero). When Algorithm 2 is invoked on this example, it terminates with a proof of validity after two refinement iterations (see Table I). The counterexample produced in the first iteration is localized by eliminating irrelevant assignments, namely those that correspond to the “else” branches of the the ite operators involving variable l as well as other assignments that depend on them. Next, the remaining relevant assignments are generalized into the violation constraint a 0 l 1 t u which, in this case, cannot be enlarged further using MUS extraction from the abstract formula. Upon checking this violation constraint on the concrete formula it is found to be spurious, and leads to the creation of two simpler explanations: 1) the least significant bit of a cannot be 1 when a is 0, and 2) shifting b right by two bits is equivalent to concatenating zeros to the left of b’s two most significant bits. The abstract formula is now refined to eliminate these two violations, i.e., at the start of the second iteration the correctness condition is checked against abst a 0 l 1 t u . In the second iteration, localization is unable to eliminate any assignments from the counterexample. However, generalization retains only three of the assignments as well as the equality between t and u from the first iteration, and deduces that a and s are not equal. MUS extraction identifies that the assignment to m is immaterial to the current violation and can be safely removed. Checking this violation constraint on the concrete formula shows that it is still spurious, and identifies the

We implemented the above refinement strategies in the Reveal system which performs verification of hardware designs using datapath abstraction. Reveal consists of the following components: Vapor [2] for abstracting designs written in behavioral Verilog to the UCLID language. UCLID [6] for converting the abstracted design to a formula in the CLU logic. Wave for encoding the CLU formula in propositional logic, specifically in the conjunctive normal form suitable for SAT solvers [7]. zCore and zMinimal [23] for extracting a single MUS from a CNF instance. To obtain an MUS from the abstract model, we convert the CLU expression in Algorithm 2 (line 5c) to a CNF instance using Ackerman encoding [1]. CAMUS [19] for extracting one or more MUSes from a CNF instance. We ran the experiments on an 64-bit 2.4-GHz AMD processor with 4GB of RAM running Linux. To establish a baseline, we ran Algorithm 2 by disabling MUS extraction from both the abstract (line 5c) as well as the concrete (line 8a) formulas. In all cases, the procedure had to be aborted, even for simple designs, suggesting that MUS extraction is essential for refinement. We then ran another set of experiments in which localization and generalization were disabled forcing MUS extraction to be based on the specific counterexamples produced. Again, verification failed to finish in the allotted time in all tested cases, suggesting that localization and generalization are also essential for effective refinement. We then performed a series of experiments using different combinations of MUS-based refinements with localization and generalization enabled. For ease of exposition, we will use refine(x, y) to denote refinement with: x {0,1} MUSes extracted using the abstract formula y {0,1, some, all} MUSes extracted using the concrete formula We used zCore and zMinimal to extract single MUSes, and CAMUS to extract multiple and all MUSes. The number of MUSes produced by CAMUS in the “multiple” mode can be controlled by a user-specified parameter and is typically between 3 and 7. Table II shows the results of verifying two different properties on the PDLX benchmark [25] with various refinement combinations. This benchmark consists of 686 Verilog lines and 396 latches. In the first set of experi-


TABLE II PDLX REFINEMENT RESULTS refine(0, y) T refine(x, 0) refine(x, 1) refine(x, some) refine(x, all) I M T refine(1, y) I M




T.O. T.O. T.O. T.O.

>9 >37 >7 >1

N/A >37 >25 –

T.O. T.O. 138 T.O.

>7 >22 2 >1

>7 >22 10 –

Buggy PDLX implementation; prop = (RFSpec = RFImpl) refine(0, y) T refine(x, 0) refine(x, 1) refine(x, some) refine(x, all) I M T refine(1, y) I M

T.O. 316 404 T.O.

>13 25 5 >1

N/A 25 21 –

T.O. 180 64 T.O.

>10 N/A 8 1 >1 8 4 –

Bug-free PDLX implementation; prop = (PCSpec = PCImpl)

ments, the property being checked is the equivalence between the implementation and specification register files using a buggy implementation in which the ALU output is stuck at 0. In the second set of experiments, the correctness condition is the equivalence of the implementation and specification program counters; the implementation in these experiments was bug-free. Both of these criteria are based on the Burch and Dill [8] correspondence checking scheme of pipelined microprocessors. The columns in the table give the total verification time in seconds (T), the number of refinement iterations (I) and, where applicable, the number of MUSes extracted using the concrete model (M). A time out of 600 seconds was used in all experiments. For the buggy design, the only refinement strategy that did not time out was refine(1, some). For the bugfree design, on the other hand, verification with refinements that employed one or several MUSes extracted from the concrete model finished within the allowed time. In both cases, however, the best performance was obtained with the refine(1, some) combination. Further analysis of these results reveals that the use of MUSes involves a trade-off between the effort to extract them and their effectiveness in refining the abstraction. This can be seen by comparing refine(x, all), refine(x, 1) and refine(x, some). In the first case, the excessive time needed to extract all MUSes seems to negate their utility for refinement. Comparing the other two scenarios, we note that extracting several MUSes per refinement iteration seems to always yield fewer iterations, and shorter overall verification times, than does the extraction of just one MUS in each iteration.

In this work we explored the use of MUS extraction for refinement of datapath abstractions in the CEGAR verification flow. We found that extraction of MUSes from both the abstract and concrete models is necessary for faster convergence. We also found that performance tends to improve when refinement is based on the extraction of a small number of MUSes, rather than a single MUS, from the concrete model in each iteration. Additionally, we introduced counterexample localization and generalization, and demonstrated their necessity for speeding up convergence of the refinement iteration. The robustness and scalability of the verification framework described here can be enhanced further by incorporating several additional improvements. For example, faster MUS extraction from the abstract model may be possible if the extraction algorithm were to operate directly on the abstract CLU formula rather than on its lower-level CNF Boolean encoding. Additionally, extracting multiple MUSes from the abstract model, akin to the extraction of multiple MUSes from the concrete model, may yield a further reduction in the number of refienemnt iterations and, possibly, overall verification time. Finally, by analyzing the structure of the MUSes extracted from the concrete model, it may be possible to generalize them into universal rules (templates) that can be stored in a rule base that grows with the usage of the system and that can be consulted when verifying other designs.

This work was funded in part by the DARPA/MARCO Gigascale Systems Research Center, and in part by the National Science Foundation under ITR grant No. 0205288.
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